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Analog Mixed Signal Circuit Design Engineer (Seni…

シリコンMEMSタイミングのマーケットリーダー
SiTime is seeking a talented and enthusiastic Senior or Principal Engineer to work on analog and mi…
800万円~2000万円 / リーダー

取り扱い転職エージェント

  • 勤務地

    東京都

  • 仕事内容

    SiTime is seeking a talented and enthusiastic Senior or Principal Engineer to work on analog and mixed signal ASIC design for SiTime’s industry leading timing products. SiTime Corporation a MEMS and analog semiconductor company is revolutionizing the $6 billion timing market with unique MEMS based silicon timing solutions. With 90% share of MEMS timing and over 1 billion devices shipped SiTime is driving the electronics industry’s transition to 100% silicon based timing. SiTime is headquartered in Santa Clara California and is continuing to expand with a Center of Excellence in Tokyo Japan. The Analog Mixed Signal Circuit Design Engineer (Senior or Principal) will lead and contribute to circuit design for next generation products. These products have applications ranging from high performance Networking and Communications Infrastructure to ultra low power Mobile platforms including wearable devices. Responsibilities: Develop analog and mixed signal architectures and circuits in CMOS or BiCMOS processes Analyze technology architecture circuit design and parametric design trade offs to meet aggressive technical performance specifications Perform transistor level design and simulation using industry leading EDA tools Lead comprehensive design reviews Supervise Analog Circuit Physical Design Layout and edit layouts Collaborate with Digital Design Engineers CAD Systems Engineering Test Engineering and Applications teams to ensure DFT DFM features and achieve rapid silicon bring up and time to production release Perform post layout parasitic extraction and back annotated simulations to validate design Perform requisite Monte Carlo Analysis on key circuits to ensure Six Sigma quality and yields Participate in the bring up of silicon prototypes Initiate Design of Experiments for Root Cause Analysis investigate anomalous observations in silicon across PVT conditions and propose solutions

  • 応募資格

    【Requirements】 B.Sc. with 8 years of experience or M.Sc. with 3 years of experience or Ph.D. with 1 years of experience in Electrical Engineering Proven track record at each stage of the following: o Circuit architecture development and technical feasibility studies o Writing detailed block level specifications and review documents o Detailed design and simulation of one or more of the following: Oscillators ADCs DACs temperature sensors Integer and Fractional N PLLs Digital PLLs low noise op amps regulators bandgap circuits in CMOS or BiCMOS processes subthreshold circuits and architecture o Support product teams to take the design to production Proficiency with EDA tools including Cadence Virtuoso Spectre ADE Mixed mode AMS tools Layout XL Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers Extensive experience with post layout extraction and verifications Experience with validation characterization qualification and adherence to production release criteria Ability to communicate and work effectively with geographically dispersed teams of mixed signal digital verifications engineers Ability to work independently and drive solutions to challenging problems

  • 転職エージェント

    株式会社 ジェイエイシーリクルートメント

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NEW

Digital Design Engineer

シリコンMEMSタイミングのマーケットリーダー
We are seeking a talented and enthusiastic Engineer II or Senior Engineer to work on digital ASIC d…
800万円~2000万円 / リーダー

取り扱い転職エージェント

  • 勤務地

    東京都

  • 仕事内容

    We are seeking a talented and enthusiastic Engineer II or Senior Engineer to work on digital ASIC design for industry leading timing products. The Digital Design Engineer (Engineer II or Senior) will lead and contribute to circuit design for next generation products. These products have applications ranging from high performance Networking and Communications Infrastructure to ultra low power Mobile platforms including wearable devices. 【Responsibilities】 ・ Development and verification of digital block architectures and RTL design for various functions including control state machine IO controllers digital signal processing (DSP) and multiple clock domain interface management ・ Work with other digital or mixed signal designers to define specifications for digital blocks and interfaces ・ Analyze architecture RTL design for optimal performance area and power constraints trade offs ・ Document detailed block and top level specifications ・ Perform block level RTL design and verification using industry leading EDA tools ・ Lead comprehensive design reviews ・ Support backend design flow including RTL synthesis clock tree synthesis scan and DFT insertion place and route and netlist verification ・ Collaborate with analog design engineers CAD systems engineering test engineering and applications teams to ensure define optimal DFT DFM features and achieve rapid silicon bring up and time to production release ・ Participate in the bring up of silicon prototypes ・ Analyze circuit for failure root cause analysis investigate anomalous observations in silicon across various conditions including PVT variations and propose solutions

  • 応募資格

    【Requirements】 ・ B.Sc. with 8 years of experience or M.Sc. or Ph.D with 5 years of experience in Electrical Engineering ・ Proven track record at each stage of the following: o Digital architecture development and technical feasibility studies o Writing detailed block level specifications and review documents o Detailed design and simulation of one or more of the following: digital state machines DSP functions IO controllers multiple block interface management including multi clock domain designs microcontroller design and implementation memory and register file controllers ・ Proficiency with EDA tools and design languages including Verilog VHDL SystemVerilog ・ Extensive experience in digital block verification strategies ・ Understanding of digital design flow from architecture design to sign off ・ Experience with DSP concepts circuits architectures and implementation ・ Ability to communicate and work effectively with geographically dispersed teams of mixed signal digital layout and verifications engineers ・ Ability to work independently and drive solutions to challenging problems ・ Good understanding of modeling signal processing algorithm using Matlab or Simulink ・ Experience in performing synthesis static timing analysis and netlist verifications ・ Understanding of digital backend flow for Place Route (PNR) ・ Experience in digital DFT flow (stuck at / TDF scan insertion and ATPG) ・ Experience in complex finite state machine design

  • 転職エージェント

    株式会社 ジェイエイシーリクルートメント

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DevOps Engineer for Telecom domain Project

欧州最大のコンサルティングファーム
700万円~1000万円 / その他

取り扱い転職エージェント

  • 勤務地

    東京都

  • 仕事内容

    ■Duties and Responsibilities / 職務範囲: RAN QA department is in charge of SW Quality Assurance before production deployment and we research new virtual RAN solution including Beyond 5G and Space Mobile, To integration new solution, we deploy of OpenStack based virtualization / Docker/Kubernetes based containerization platform and data center fabric network in new solution lab environment. - Design and integrate new cloud network for particular RAN new solution with other stakeholders - E2E tracking for all the issues and ensure cloud network service availability. - Coordination with L4 team (Vendor support) for final RCA & resolution. - Knowledge transfer for new issues and solutions to other member. - Working on Cloud infra-issues (QA Lab & Global). - Root cause analysis (RCA) and providing permanent fix. - Major & Minor enhancements within Cloud infra-network. - Close collaboration with other stakeholders (e.g. RAN, IPTx) to define/confirm bugs/issues and perform the corrective act

  • 応募資格

    ■Qualifications (Mandatory) / 応募条件(必須): - Minimum 5+ years of experience supporting cloud systems. - Familiar with Kubernetes, OpenStack, virtualization, KVM, and other Cloud technologies. - Solid understanding Linux CLI operation and basic configuration (equivalent to LPIC L1 or LinuC L1). - Knowledge on container software (Kubernetes, Docker, Calico, Istio) and ecosystem. - Knowledge on basics of L2/L3 network, hardware and storage integration. - Experience using Ansible, Python or similar programming languages. ■Qualifications (Preferred) / 応募条件(歓迎): - Certified Kubernetes Administrator (CKA). - Knowledge of IP NW, IP certificate holder such as CCNA, CCNP etc - Experience of integration between RAN application and the container platform. - Experience in the operation of the container platform. - Active attitude to the new technologies and products. - Great problem solving ability.

  • 転職エージェント

    株式会社コトラ

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POS Functional Country Lead

欧州最大のコンサルティングファーム
700万円~1000万円 / その他

取り扱い転職エージェント

  • 勤務地

    東京都

  • 仕事内容

    1. Experience in Retail - Point of Sale system functions involving day-to-day store operations. 2. Core Functional understanding of Point of Sale and upstream/downstream systems. 3. Experienced in 24*7 retail stores production support, which includes providing level 2/3 support for store support and system monitoring for backend interfaces to merchandising, credit servers support and release deployment to ensure normal business continuity. 4. Knowledge on Automation process and scripting 5. .Net and PL/SQL Experience 6. Techno Functional Knowledge on RetailPOS Implementation Knowledge 7. Root Cause Analysis on issues 8. Production Support Experience and L2 delivery 9. Experience in Implementation , Development, Analysis and need to interact with process owners / SME’s on solutions 10. New Store Rollout Experience 11. Ability to handle L2/L3 fixes on ? Sales Audit\Polling ? Store Operations Management ? Inventory Management ? Settlement issues ? Pricing and

  • 応募資格

    Skills : ・POS Tool: CEGID is Preferred and if no CEGID skills are there then candidate should have any other POS (Point of Sale) Tool experience ・Database: PL/SQL ・Language : Japanese - Native level, English - Business Level (Reading documents, mails)

  • 転職エージェント

    株式会社コトラ

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