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神奈川県

最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

求める学歴：大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

求める学歴：大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

求める学歴：大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

株式会社A・ヒューマン

群馬県

【Position Summary】 ・Coordinate the necessary activities to ensure the corrective and preventive actions are implemented for the Customer's complaints. ・Responsible for improving the overall quality performance of the product we deliver to our customers. ・Strong in site support to customer for all complaints, implement effective and in time containment actions at customer location. ・Reporting line directly to Mexico dotted in Japan manager. 【Supervisory Responsibilities】 ・As a part of the supervisory responsibilities, if there is not an employee to attend the process, the direct boss will have to attend the process or assign the activities to another employee (with equal qualifications). 【Job Responsibilities】 ・Responsible for maintaining and continual improvement activities to enhance the quality system. ・Implement in time and affective containment actions at customer location. ・Ensure the Implementation of containment and corrective actions for customer complaints. ・Preparation of QA reports. ・Immediate support to customer when complaints are reported. ・Coordinate and manage sorting activities at customer location. ・Daily support at customer facilities. ・First samples delivery (CPMs, BeOns) ・Ensure release note is provided (PPAP status). ・Provide 1st level analysis for customer complaints. ・Dispute NTF and customer at fault complaints reported by customer. ・Develop strategy to achieve quality goals. ・Other activities requested by customer. ・Other activities assigned by Quality Manager

【Basic Qualifications】 ・Integrity, Innovation. Inclusion. ・Teamwork & Respect, Excellence. ・Engineering Degree (electrical, mechatronics, mechanical or Industrial.). • Advanced English, Advanced Japanese, Advanced Spanish (desired) ・5 years of prior experience in industrial product manufacturing environment. ・Management of Automotive Customer Portals. ・Experiences in Quality assurance with electronic domain knowledge and component will be head units and amps in cars. ・Knowledge of VDA 6.3, IATF16949:2016. ・Ability to travel up to 50%, travel could be both domestic and international. 【Preferred Qualifications】 ・Leadership, Change Orientation, Collaboration, Judgment. ・Result Driven, Analytical. ・Communication Skills (Oral and Written). ・Ability to plan and organize. ・Initiative, Problem solving skills. ・Computer knowledge (Auto cad, Office: Word, Excel, Power Point, SAP, etc.).

株式会社A・ヒューマン

神奈川県

Physical Design Engineer （ASIC/SoC Place ＆ Route） Responsibilities: Perform the following: o Chip/Block level floorplan, o Clock tree synthesis, o Place ＆ Route, o RC extraction, o STA, timing closure, o IR/EM analysis and fix, o DRC/LVS/ERC analysis and fix, o Tape－out sign off. Customer on－site support.

Requirements: o Bachelor/Master’s degree in Electrical Engineering or Computer Science. 5－15 years Netlist （or RTL）－GDS physical implementation experience. Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. In depth knowledge of major EDA tools/design flows. Experience with below technology. Experience in block level implementation, chip integration and signoff. Experience in Perl/TCL language programming. Proven record in multi－million gate design production tapeouts. Experience in any of the following is a plus: o FinFet Design o Low－power implementation methodology. o Advanced timing signoff methodology. o Independently complete Netlist－GDS P＆R, signoff task. Personal Attributes: o Aggressive in learning and problem－solving. o Good communication skill and a good team player. o Strong project ownership and commitment. o Self－motivated and can work independently.

HRC株式会社