取り扱い人材紹介会社
神奈川県
最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.
求める学歴:大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.
株式会社A・ヒューマン
取り扱い人材紹介会社
神奈川県
最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.
求める学歴:大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.
株式会社A・ヒューマン
取り扱い人材紹介会社
神奈川県
最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.
求める学歴:大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.
株式会社A・ヒューマン
取り扱い人材紹介会社
神奈川県
Physical Design Engineer (ASIC/SoC Place & Route) Responsibilities: Perform the following: o Chip/Block level floorplan, o Clock tree synthesis, o Place & Route, o RC extraction, o STA, timing closure, o IR/EM analysis and fix, o DRC/LVS/ERC analysis and fix, o Tape-out sign off. Customer on-site support.
Requirements: o Bachelor/Master’s degree in Electrical Engineering or Computer Science. 5-15 years Netlist (or RTL)-GDS physical implementation experience. Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. In depth knowledge of major EDA tools/design flows. Experience with below technology. Experience in block level implementation, chip integration and signoff. Experience in Perl/TCL language programming. Proven record in multi-million gate design production tapeouts. Experience in any of the following is a plus: o FinFet Design o Low-power implementation methodology. o Advanced timing signoff methodology. o Independently complete Netlist-GDS P&R, signoff task. Personal Attributes: o Aggressive in learning and problem-solving. o Good communication skill and a good team player. o Strong project ownership and commitment. o Self-motivated and can work independently.
HRC株式会社
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