GDS physical implementation experienceの転職・求人検索結果

該当求人件数: 5件

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最大手ファンダリーのPhysical Design Manager & Enginee

非公開
1000万円~1199万円 / メンバー

取り扱い人材紹介会社

圓山 孝一
  • 勤務地

    神奈川県

  • 仕事内容

    最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

  • 応募資格

    求める学歴:大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

  • 人材紹介会社

    株式会社A・ヒューマン

気になる 詳細を見る

最大手ファンダリーのPhysical Design Manager & Engineer

非公開
900万円~1099万円 / メンバー

取り扱い人材紹介会社

圓山 孝一
  • 勤務地

    神奈川県

  • 仕事内容

    最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

  • 応募資格

    求める学歴:大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

  • 人材紹介会社

    株式会社A・ヒューマン

気になる 詳細を見る

最大手ファンダリーのPhysical Design Manager & Engineer

非公開
700万円~899万円 / メンバー

取り扱い人材紹介会社

圓山 孝一
  • 勤務地

    神奈川県

  • 仕事内容

    最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: Chip/Block level floorplan, Clock tree synthesis, Place & Route, RC extraction, STA, timing closure, IR/EM analysis and fix, DRC/LVS/ERC analysis and fix, Tapeout sign off. Customer onsite support.

  • 応募資格

    求める学歴:大学卒以上 Requirements: *Education: Bachelor/Master’s degree in Electrical Engineering or Computer Science. *515 years Netlist (or RTL)GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multimillion gate design production tapeouts. *Experience in any of the following is a plus: FinFet Design TSMC N7 and below technology. Lowpower implementation methodology. Advanced timing signoff methodology. Independently complete NetlistGDS P&R, signoff task.・中国語が話せれば尚可

  • 人材紹介会社

    株式会社A・ヒューマン

気になる 詳細を見る

Physical Design Manager & Engineer

外資系半導体メーカー
800万円~1200万円 / メンバー

取り扱い人材紹介会社

松垣 潔
  • 勤務地

    神奈川県

  • 仕事内容

    Physical Design Engineer (ASIC/SoC Place & Route) Responsibilities: Perform the following: o Chip/Block level floorplan, o Clock tree synthesis, o Place & Route, o RC extraction, o STA, timing closure, o IR/EM analysis and fix, o DRC/LVS/ERC analysis and fix, o Tape-out sign off. Customer on-site support.

  • 応募資格

    Requirements: o Bachelor/Master’s degree in Electrical Engineering or Computer Science. 5-15 years Netlist (or RTL)-GDS physical implementation experience. Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. In depth knowledge of major EDA tools/design flows. Experience with below technology. Experience in block level implementation, chip integration and signoff. Experience in Perl/TCL language programming. Proven record in multi-million gate design production tapeouts. Experience in any of the following is a plus: o FinFet Design o Low-power implementation methodology. o Advanced timing signoff methodology. o Independently complete Netlist-GDS P&R, signoff task. Personal Attributes: o Aggressive in learning and problem-solving. o Good communication skill and a good team player. o Strong project ownership and commitment. o Self-motivated and can work independently.

  • 人材紹介会社

    HRC株式会社

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【神奈川】Physical Design Manager & Engineer

外資系半導体メーカー
年収800~1200万円
800万円~1200万円 / メンバー

取り扱い人材紹介会社

松垣 潔
  • 勤務地

    神奈川県

  • 仕事内容

    Physical Design Engineer (ASIC/SoC Place & Route) Responsibilities: Perform the following: o Chip/Block level floorplan, o Clock tree synthesis, o Place & Route, o RC extraction, o STA, timing closure, o IR/EM analysis and fix, o DRC/LVS/ERC analysis and fix, o Tape-out sign off. Customer on-site support.

  • 応募資格

    Requirements: o Bachelor/Master’s degree in Electrical Engineering or Computer Science. 5-15 years Netlist (or RTL)-GDS physical implementation experience. Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. In depth knowledge of major EDA tools/design flows. Experience with below technology. Experience in block level implementation, chip integration and signoff. Experience in Perl/TCL language programming. Proven record in multi-million gate design production tapeouts. Experience in any of the following is a plus: o FinFet Design o Low-power implementation methodology. o Advanced timing signoff methodology. o Independently complete Netlist-GDS P&R, signoff task. Personal Attributes: o Aggressive in learning and problem-solving. o Good communication skill and a good team player. o Strong project ownership and commitment. o Self-motivated and can work independently.

  • 人材紹介会社

    HRC株式会社

気になる 詳細を見る

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  • 1

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