Tcl/Tkの転職・求人検索結果

大阪府 ／ 神奈川県

Responsibilities: ・Lead innovation and enablement of custom design methodology and solutions to address critical design challenges in leading edge technologies. ・Collaborate with EDA partners to deliver innovative and comprehensive design solutions and PDK’s for analog/mixed signal/RF designers. ・Lead and conduct custom design tool and flow certification.

Requirements: ・Education: 　BCH degree and above in Electrical/Computer Engineering or Computer Science with minimum 3 years of industry experience. ・Must have industry experience in custom design flow custom circuit design and/or Process Design Kit （PDK） development. ・Familiar with custom design flow and related EDA tools including physical verification RC extraction Custom place N route reliability analysis and SPICE simulation. the following experience is plus ・Experience in design methodologies for custom digital analog and RF circuits and layout designs ・Experience in custom layout tools （Virtuoso Custom Compiler） ・Experience in circuit simulation tools for analog and RF circuits （Spectre HSPICE PrimeSim …） ・Experience in node to node migration flow ・In depth understanding and usage of Foundry PDK’s. ・Strong scripting skills in C SHELL Python TCL and Cadence SKILL programming. ・Strong customer orientation and good communication skills are highly desirable. ・Good working knowledge of Analog /RF circuits.

株式会社 ジェイエイシーリクルートメント

神奈川県

２，ロジック設計・ロジック回路設計・論理検証・バックエンド設計 ＜担当製品＞車載用CMOSイメージセンサー　 ●EDAツール・Mentor社 Tessent (TestKompress, BoundaryScan, MemoryBIST, LogicBIST, IJTAGなど) ・Synopsys社 DFT-Compiler, TetraMAX, VCS, Formality, DesignCompiler, Verdiなど）利用言語: Verilog/VHDL, Tcl, B/C-shell　 【リモートワーク対応中】

【必須】※以下いずれかに該当する方　 ・LSI設計・LSI検証もしくは評価実務経験 ●教育には本気です：メンバの声を聞きながらテーマや運営方法は都度改善。オンラインで実施。 ▼動画研修「量子コンピューティング」「メタバース」など ▼ナレッジ共有会（過去発表したテーマ）：「物体検出アルゴリズムyoloについて」「Appiumを用いたテスト自動化について」「エッジコンピューティング」など ▼チーム勉強会：「AWS・AI」「IoTデバイス」「3次元積層集積回路」などチームごとにテーマを決め勉強実施。

リクルートエージェント（株式会社リクルート）

神奈川県

最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

求める学歴：大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのAPR （Automatic Place& Route) Manager/EngineerResponsibilities: *Physical design implementation *APR flow development *Advanced APR solution path finding

◆学歴 ・大学卒以上 ◆経験・スキル Requirements: *Education: - Master or PhD Computer engineering or EE * APR chip implementation experience with advanced process nodes (28nm and below) *Familiar with P&R and timing signoff * Familiar with Script languages (shell, python, TCL) or C/C++ * Fluent in English speaking *Mathematical is also okay and willing to learn APR and research for new APR flow (Optional) * Language: - Proficiency in English is basic requirement. Proficiency in Chinese is a plus. * Specific Requirement: - APR Engineer: Seniority > 5 years. Full chip integration experience is a plus. - APR Lead Manager: Seniority> 15 years. Experienced with full chip integration/signoff and tape-out management is needed. ◆英語スキル ・ビジネスレベル

株式会社A・ヒューマン

東京都

外資系ネットワークベンダーのシステム・エンジニア当社のネットワーク製品、特に、Application　Firewall、WAF、DDoS対策等のセキュリティソリューションに関するプリセールスを担っていただきます。 　・製品やソリューションのプレゼンテーション 　・デモンストレーション 　・導入に関する技術的サポート 　・トラブルシューティングの支援　等

【求める学歴】 大卒以上 【求める経験・スキル（全てでなくても可）】 ・Network Layer-4-7の知識（HTTP, DNS, SSL, and Caching、パケット分析等） ・Web侵入テストツールなどの知見（burp suite, zed attack proxy等） ・WAF/IDS/IPS 等の取り扱い経験 ・UNIX/LINUX サーバー環境の構築スキル ・スクリプト言語の知見（Python 、Tcl等） 【英語スキル】 ・ビジネスレベルが望ましい

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのAPR （Automatic Place& Route) Manager/EngineerResponsibilities: *Physical design implementation *APR flow development *Advanced APR solution path finding

◆学歴 ・大学卒以上 ◆経験・スキル Requirements: *Education: - Master or PhD Computer engineering or EE * APR chip implementation experience with advanced process nodes (28nm and below) *Familiar with P&R and timing signoff * Familiar with Script languages (shell, python, TCL) or C/C++ * Fluent in English speaking *Mathematical is also okay and willing to learn APR and research for new APR flow (Optional) * Language: - Proficiency in English is basic requirement. Proficiency in Chinese is a plus. * Specific Requirement: - APR Engineer: Seniority > 5 years. Full chip integration experience is a plus. - APR Lead Manager: Seniority> 15 years. Experienced with full chip integration/signoff and tape-out management is needed. ◆英語スキル ・ビジネスレベル

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: Chip/Block level floorplan, Clock tree synthesis, Place & Route, RC extraction, STA, timing closure, IR/EM analysis and fix, DRC/LVS/ERC analysis and fix, Tapeout sign off. Customer onsite support.

求める学歴：大学卒以上 Requirements: *Education: Bachelor/Master’s degree in Electrical Engineering or Computer Science. *515 years Netlist (or RTL)GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multimillion gate design production tapeouts. *Experience in any of the following is a plus: FinFet Design TSMC N7 and below technology. Lowpower implementation methodology. Advanced timing signoff methodology. Independently complete NetlistGDS P&R, signoff task.・中国語が話せれば尚可

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのAPR （Automatic Place& Route) Manager/EngineerResponsibilities: *Physical design implementation *APR flow development *Advanced APR solution path finding

◆学歴 ・大学卒以上 ◆経験・スキル Requirements: *Education: - Master or PhD Computer engineering or EE * APR chip implementation experience with advanced process nodes (28nm and below) *Familiar with P&R and timing signoff * Familiar with Script languages (shell, python, TCL) or C/C++ * Fluent in English speaking *Mathematical is also okay and willing to learn APR and research for new APR flow (Optional) * Language: - Proficiency in English is basic requirement. Proficiency in Chinese is a plus. * Specific Requirement: - APR Engineer: Seniority > 5 years. Full chip integration experience is a plus. - APR Lead Manager: Seniority> 15 years. Experienced with full chip integration/signoff and tape-out management is needed. ◆英語スキル ・ビジネスレベル

株式会社A・ヒューマン

神奈川県

最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities: *Perform the following: - Chip/Block level floorplan, - Clock tree synthesis, - Place & Route, - RC extraction, - STA, timing closure, - IR/EM analysis and fix, - DRC/LVS/ERC analysis and fix, - Tape-out sign off. - Customer on-site support.

求める学歴：大学卒以上 Requirements: *Education: - Bachelor/Master’s degree in Electrical Engineering or Computer Science. *5-15 years Netlist (or RTL)-GDS physical implementation experience. *Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus. *In depth knowledge of major EDA tools/design flows. *Experience with TSMC N16 or below technology. *Experience in block level implementation, chip integration and signoff. *Experience in Perl/TCL language programming. *Proven record in multi-million gate design production tapeouts. *Experience in any of the following is a plus: - FinFet Design - TSMC N7 and below technology. - Low-power implementation methodology. - Advanced timing signoff methodology. - Independently complete Netlist-GDS P&R, signoff task.

株式会社A・ヒューマン

東京都

Responsibilities: Develop and support functional verification platform for multiple MCU (Micro Control Unit) and SoC (System on a Chip) projects. - Developing functional verification platform and verification technologies - Supporting MCU/SoC design engineers with the verification platform and the verification technologies - Leading members of the verification platform team

Background of Recruitment: The efficiency of functional verification is a key factor which greatly determines MCU/SoC time-to-market. We develop and provide our own functional verification platform and the related verification technologies for improving the efficiency and the quality of functional verification to contribute to Renesas MCU/SoC product value. Responsibilities: Develop and support functional verification platform for multiple MCU (Micro Control Unit) and SoC (System on a Chip) projects. - Developing functional verification platform and verification technologies - Supporting MCU/SoC design engineers with the verification platform and the verification technologies - Leading members of the verification platform team Required Skills and Work Experience: MUST - Basic Knowledge about RTL design&verification process and Verilog-HDL - Basic programming abilities (ex. Linux, shell script, Perl, Tcl, C/C++ etc) - Work experience about a development team leading - Negoti

株式会社コトラ

神奈川県

・チップもしくはブロックレベルの配置設計、配線配置 ・クロックツリー合成 ・RC抽出 ・STA、タイミング収束 ・電圧降下（IR Drop）、電流密度（EM）の分析及び修正 ・デザインルールチェック(DRC)、レイアウト検証 (LVS)、ERC（electrical rule checking）の分析及び修正 ・テープアウトのサインオフ ・APR(Automatic Place& Route)フロー開発

・電気電子、化学系 出身 ・デジタル設計、設計フロー、APRチップ実装関連分野で3年以上の実務経験。 ・28nm以下のプロセス経験 ・スクリプト言語（Shell、Python、TCL）またはC/ C++の知識 ・APRツール(Cadence InnovusやSynopsys IC Compilerなど)の知識

キャリア・デベロプメント・アソシエイツ株式会社