Digital Design Engineer

募集要項

• こだわり条件

  設立50年以上 語学（英語）を生かす 年間休日120日以上 土日祝日休み

• 仕事内容

  We are seeking a talented and enthusiastic Engineer II or Senior Engineer to work on digital ASIC design for industry leading timing products.
  
  The Digital Design Engineer （Engineer II or Senior） will lead and contribute to circuit design for next generation products. These products have applications ranging from high performance Networking and Communications Infrastructure to ultra low power Mobile platforms including wearable devices.
  
  【Responsibilities】
  ・ Development and verification of digital block architectures and RTL design for various functions including control state machine IO controllers digital signal processing （DSP） and multiple clock domain interface management
  ・ Work with other digital or mixed signal designers to define specifications for digital blocks and interfaces
  ・ Analyze architecture RTL design for optimal performance area and power constraints trade offs
  ・ Document detailed block and top level specifications
  ・ Perform block level RTL design and verification using industry leading EDA tools
  ・ Lead comprehensive design reviews
  ・ Support backend design flow including RTL synthesis clock tree synthesis scan and DFT insertion place and route and netlist verification
  ・ Collaborate with analog design engineers CAD systems engineering test engineering and applications teams to ensure define optimal DFT DFM features and achieve rapid silicon bring up and time to production release
  ・ Participate in the bring up of silicon prototypes
  ・ Analyze circuit for failure root cause analysis investigate anomalous observations in silicon across various conditions including PVT variations and propose solutions

• 職種分類

  電気・電子・機械系エンジニア ＞ 電気・電子・半導体系 ＞ 研究・開発・設計（電気・電子・半導体）

• 業種分類

  電気・電子・半導体

• 応募条件

  【Requirements】
  ・ B.Sc. with 8 years of experience or M.Sc. or Ph.D with 5 years of experience in Electrical Engineering
  ・ Proven track record at each stage of the following:
  o Digital architecture development and technical feasibility studies
  o Writing detailed block level specifications and review documents
  o Detailed design and simulation of one or more of the following: digital state machines DSP functions IO controllers multiple block interface management including multi clock domain designs microcontroller design and implementation memory and register file controllers
  ・ Proficiency with EDA tools and design languages including Verilog VHDL SystemVerilog
  ・ Extensive experience in digital block verification strategies
  ・ Understanding of digital design flow from architecture design to sign off
  ・ Experience with DSP concepts circuits architectures and implementation
  ・ Ability to communicate and work effectively with geographically dispersed teams of mixed signal digital layout and verifications engineers
  ・ Ability to work independently and drive solutions to challenging problems
  ・ Good understanding of modeling signal processing algorithm using Matlab or Simulink
  ・ Experience in performing synthesis static timing analysis and netlist verifications
  ・ Understanding of digital backend flow for Place Route （PNR）
  ・ Experience in digital DFT flow （stuck at / TDF scan insertion and ATPG）
  ・ Experience in complex finite state machine design

• 年収

  800万円～2000万円
  800万円 - 2000万円

• ポジション

  リーダー

• 雇用形態

  正社員

• 勤務地

  東京都

• 勤務地（市区町村）

  港区

• 勤務時間

  09:00 ～ 18:00

• 休日・休暇

  【有給休暇】初年度 10日 4か月目から
  【休日】完全週休二日制
  土
  日
  祝日
  GW
  年末年始
  

• 福利厚生

  【通勤手当】全額支給
  【社会保険】健康保険
  雇用保険
  労災保険
  

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